Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-27
MOB Load
Replays
The number of
replayed loads
related to the
Memory Order Buffer
(MOB). This metric
counts only the case
where the
store-forwarding
data is not an aligned
subset of the stored
data.
MOB_load_replay PARTIAL_DATA,
UNALGN_ADDR
2
nd-
Level
Cache Read
Misses
2
The number of
2nd-level cache read
misses (load and
RFO misses).
Beware of granularity
differences.
BSQ_cache_reference RD_2ndL_MISS
2
nd-
Level
Cache Read
References
2
The number of
2nd-level cache read
references (loads
and RFOs). Beware
of granularity
differences.
BSQ_cache_reference RD_2ndL_HITS,
RD_2ndL_HITE,
RD_2ndL_HITM,
RD_2ndL_MISS
3rd-Level
Cache Read
Misses
2
The number of
3rd-level cache read
misses (load and
RFOs misses).
Beware of granularity
differences.
BSQ_cache_reference RD_3rdL_MISS
3
rd-
Level Cache
Read
References
2
The number of
3rd-level cache read
references (loads
and RFOs). Beware
of granularity
differences.
BSQ_cache_reference RD_3rdL_HITS,
RD_3rdL_HITE,
RD_3rdL_HITM,
RD_3rdL_MISS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)