Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-36
Bus Reads
Underway from
the processor
7
This is an accrued
sum of the durations
of all read (includes
RFOs) transactions
by this processor.
Divide by “Reads
from the Processor”
to get bus read
request latency. Also
Beware of different
recipes in mask bits
for Pentium 4 and
Intel Xeon
processors between
CPUID model field
value of 2 and model
value less than 2.
IOQ_active_entries 1a. ReqA0,
ALL_READ,
OWN, PREFETCH
(CPUID model <
2);
1b. ReqA0,
ALL_READ,
MEM_WB, MEM_WT,
MEM_WP, MEM_WC,
MEM_UC,
OWN, PREFETCH
(CPUID model >=
2);
Non-prefetch
Reads
Underway from
the processor
7
This is an accrued
sum of the durations
of read (includes
RFOs but excludes
prefetches) transac-
tions that originate
from this processor.
Divide by “Reads
Non-prefetch from
the processor” to get
Non-prefetch read
request latency. Also
Beware of different
recipes in mask bits
for Pentium 4 and
Intel Xeon processors
between CPUID
model field value of 2
and model value less
than 2.
IOQ_active_entries 1a. ReqA0
,
ALL_READ, OWN
(CPUID model <
2);
1b. ReqA0,
ALL_READ,
MEM_WB, MEM_WT,
MEM_WP, MEM_WC,
MEM_UC, OWN
(CPUID model >=
2).
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)