Intel ARCHITECTURE IA-32 User Manual

IA-32 Instruction Latency and Throughput C
C-21
For the sake of simplicity, all data being requested is assumed to reside
in the first level data cache (cache hit). In general, IA-32 instructions
with load operations that execute in the integer ALU units require two
more clock cycles than the corresponding register-to-register flavor of
the same instruction. Throughput of these instructions with load
operation remains the same with the register-to-register flavor of the
instructions.
Floating-point, MMX technology, Streaming SIMD Extensions and
Streaming SIMD Extension 2 instructions with load operations require 6
more clocks in latency than the register-only version of the instructions,
but throughput remains the same.
When store operations are on the critical path, their results can generally
be forwarded to a dependent load in as few as zero cycles. Thus, the
latency to complete and store isn’t relevant here.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)