Intel ARCHITECTURE IA-32 User Manual

Stack Alignment D
D-8
// the goal is to make
esp and ebp
// (0 mod 16) here
j = k;
mov edx, [ebx + 8] // k is (0 mod 16) if
caller aligned
// its stack
mov [ebp - 16], edx // J is (0 mod 16)
foo(5);
add esp, -4 // normal call sequence
to
// unaligned entry
mov [esp],5
call foo // for stdcall, callee
// cleans up stack
foo.aligned(5);
add esp,-16 // aligned entry, this
should
// be a multiple of 16
mov [esp],5
call foo.aligned
add esp,12 // see Note B
return j;
mov eax,[ebp-16]
pop edx
mov esp,ebp
pop ebp
mov esp,ebx
pop ebx
ret 4
}
Example D-2 Aligned ebp-based Stack Frames (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)