Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
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when data is written back to memory, the eviction consumes cache
bandwidth and bus bandwidth. For multiple cache misses that require
the eviction of modified lines and are within a short time, there is an
overall degradation in response time of these cache misses.
For store operation, reading for ownership must be completed before the
data is written to the first-level data cache and the line is marked as
modified. Reading for ownership and storing the data happens after
instruction retirement and follows the order of retirement. The bus store
latency does not affect the store instruction itself. However, several
sequential stores may have cumulative latency that can effect
performance.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)