Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-16
Assembly/Compiler Coding Rule 1. (MH impact, H generality) Arrange
code to make basic blocks contiguous and eliminate unnecessary branches.
For the Pentium M processor, every branch counts, even correctly
predicted branches have a negative effect on the amount of useful code
delivered to the processor. Also, taken branches consume space in the
branch prediction structures and extra branches create pressure on the
capacity of the structures.
Assembly/Compiler Coding Rule 2. (M impact, ML generality) Use the
setcc and cmov instructions to eliminate unpredictable conditional branches
where possible. Do not do this for predictable branches. Do not use these
instructions to eliminate all unpredictable conditional branches (because using
these instructions will incur execution overhead due to the requirement for
executing both paths of a conditional branch). In addition, converting
conditional branches to
cmovs or setcc trades of control flow dependence for
data dependence and restricts the capability of the out of order engine. When
tuning, note that all IA-32 based processors have very high branch prediction
rates. Consistently mispredicted are rare. Use these instructions only if the
increase in computation time is less than the expected cost of a mispredicted
branch.
Consider a line of C code that has a condition dependent upon one of the
constants:
X = (A < B) ? CONST1 : CONST2;
This code conditionally compares two values, A and B. If the condition is
true,
X is set to CONST1; otherwise it is set to CONST2. An assembly code
sequence equivalent to the above C code can contain branches that are
not predictable if there are no correlation in the two values.
Example 2-1 shows the assembly code with unpredictable branches.
The unpredictable branches in Example 2-1 can be removed with the
use of the
setcc instruction. Example 2-2 shows an optimized code that
does not have branches.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)