Freescale Semiconductor MPC5604B

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MPC5604B/C Microcontroller Reference Manual, Rev. 8

Freescale Semiconductor 143

0xC3FD

_C068

ME_PS2

S_PIT_RTI

S_RTC_API

S_eMIOS1

S_eMIOS0

S_WKPU

S_SIUL

0xC3FD

_C06C

ME_PS3 R

S_CMU

0xC3FD

_C070

reserved

0xC3FD

_C074

…

0xC3FD

_C07C

reserved

0xC3FD

_C080

…

0xC3FD

_C09C

ME_RUN_PC

0…7

R0 0 0 0 0000000 00000

R0 0 0 0 0000

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

0xC3FD

_C0A0

…

0xC3FD

_C0BC

ME_LP_PC0

…7

R0 0 0 0 0000000 00000

R0 0

STANDBY

STOP

HALT

00000000

Table 8-3. MC_ME Memory Map (continued)

Address Name

012327567891011 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Main Page

Default Chapter14
- Table of Contents14
- Overview30
Appendix B33
Revision History33
- References34
Chapter 1 Reference Manual Content35
- Using the MPC5604B36
  - Input/Output Pins37
  - Software Design38
- The MPC5604B Microcontroller Family40
- Block Diagram43
Chapter 2 Chip-Level Features44
- Packages45
- Introduction50
Chapter 353
Chapter 453
- Pad Configuration During Reset Phases53
- Voltage Supply Pins54
- System Pins55
- Nexus 2+ Pins72
- Boot Mechanism74
Chapter 575
- Flash Memory Boot75
- Serial Boot Mode77
- Boot Assist Module (BAM)82
  - Linflex (RS232) Boot90
  - Flexcan Boot91
- System Status and Configuration Module (SSCM)93
- Modes of Operation94
Chapter 6104
- Clock Architecture104
- Clock Gating105
- Fast External Crystal Oscillator (FXOSC) Digital Interface106
- Register Description107
- Slow External Crystal Oscillator (SXOSC) Digital Interface108
- Register Description109
- Slow Internal RC Oscillator (SIRC) Digital Interface110
- Register Description111
- Fast Internal RC Oscillator (FIRC) Digital Interface112
- Main Features122
- Functional Description123
- Memory Map and Register Description125
- Overview130
Chapter 7141
- Output Clock Multiplexing141
- Output Clock Division Selection142
Chapter 8178
- Modes Details178
- Mode Transition Process183
- Protection of Mode Configuration Registers193
- Peripheral Clock Gating195
- Application Example196
- Destructive Resets218
- Functional Resets219
- Boot Mode Capturing220
- Initialization Information232
Chapter 10 Voltage Regulators234
Chapter 11 Ultra Low Power Regulator (ULPREG)235
- Register Description236
- Power Domain Organization237
  - Overview240
  - Features242
Chapter 12243
- NMI Status Flag Register (NSR)243
- NMI Configuration Register (NCR)244
- Wakeup/Interrupt Status Flag Register (WISR)245
- Interrupt Request Enable Register (IRER)246
- Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER)247
- Wakeup/Interrupt Filter Enable Register (WIFER)248
- Functional Description249
- External Wakeups/Interrupts251
- On-Chip Wakeups252
- Overview254
Chapter 13 Device-Specific Information256
- Debug Mode257
- RTC Control Register (RTCC)258
- RTC Status Register (RTCS)260
- RTC Counter Register (RTCCNT)261
- API Functional Description262
Chapter 14268
- Baud Rate Generation268
- Overview272
Chapter 17274
- Block Diagram274
  - Instruction Unit Features275
  - Load/Store Unit Features276
- Core Registers and Programmer's Model277
Chapter 16300
- Interrupt Request Sources300
- Handshaking with Processor302
- Initialization/Application Information304
- ISR, RTOS, and Task Hierarchy306
- Order of Execution307
- Priority Ceiling Protocol308
- Software Configurable Interrupt Requests309
- Lowering Priority Within an ISR310
- Examining LIFO Contents311
  - Introduction312
  - Overview313
- General Operation314
- Slave Ports315
Chapter 18 Putting It All Together and AHB Error Terminations335
- Introduction338
- Features340
Chapter 19341
- Detailed Signal Descriptions341
- Memory Map and Register Description342
- Pin Muxing363
- Introduction366
- Block Diagram367
- General Description389
- Fractional Baud Rate Generation390
Chapter 21 LIN Mode422
- Bit Timeout Counter430
- Interrupts432
- Introduction434
- Flexcan Module Features435
- Modes of Operation436
- Signal Descriptions437
- Message Buffer Structure439
- Local Priority Transmission463
- Arbitration Process464
- Receive Process465
- Matching Process466
- Data Coherence467
- Rx FIFO470
- CAN Protocol Related Features471
- Flexcan Addressing and SRAM Size Configurations478
Chapter 23483
- Debug Mode483
- Memory Map and Register Description485
- DSPI Module Configuration Register (Dspix_Mcr)486
- DSPI Transfer Count Register (Dspix_Tcr)489
- DSPI Status Register (Dspix_Sr)497
- DSPI Interrupt Request Enable Register (Dspix_Rser)499
- DSPI PUSH TX FIFO Register (Dspix_Pushr)501
- DSPI POP RX FIFO Register (Dspix_Popr)503
- DSPI Transmit FIFO Registers 0–3 (Dspix_Txfrn)504
- Functional Description505
- Modes of Operation506
- Initialization and Application Information527
  - Delay Settings529
Chapter 24 Timers532
- Introduction534
- Overview of the STM536
- Overview of the PIT538
- External Signal Description539
- Functional Description543
- External Signal Description546
- Functional Description558
- Initialization/Application Information588
- Periodic Interrupt Timer (PIT)591
- Features592
  - Functional Description597
  - Initialization and Application Information598
- Overview602
Chapter 25603
- Device-Specific Implementation603
- Functional Description604
- Analog Clock Generator and Conversion Timings608
- ADC CTU (Cross Triggering Unit)610
- Presampling611
- Programmable Analog Watchdog612
- Interrupts613
- External Decode Signals Delay614
- Register Descriptions615
- Control Logic Registers618
- Interrupt Registers622
- Threshold Registers629
- Presampling Registers630
- Mask Registers633
- Delay Registers638
- Data Registers639
- Introduction642
- Functional Description644
Chapter 26 Channel Value646
Chapter 32650
- Introduction650
- Main Features651
- Functional Description652
- Reset657
- Programming Considerations714
  - Double Word Program715
  - Sector Erase717
- Platform Flash Memory Controller725
- Memory Map and Register Description728
- Functional Description737
- Introduction746
Chapter 28747
- Access Timing747
- Reset Effects on SRAM Accesses748
- Introduction752
- Modes of Operation753
  - Memory Map754
Chapter 31755
- Register Description755
- Functional Description757
  - Access Errors761
Chapter 30766
- Overview766
- External Signal Description767
  - Register Description768
  - Functional Description772
Chapter 27774
- Introduction774
  - Register Description775
  - Register Protection794
Chapter 29798
- Introduction798
- Features799
- External Signal Description800
- Memory Map and Register Description801
- Features813
- Modes of Operation814
Chapter 33 Operating Mode815
- Nexus Debug Interface Registers816
- Register Description817
- Functional Description826
- Enabling Nexus Clients for TAP Access827
- Configuring the NDI for Nexus Messaging828
- Debug Mode Control829
Appendix A832
- Register Map833
- Register Map834
- Register Map835
- Register Map836
- Register Map837
- Register Map838
- Register Map839
- Register Map840
- Register Map841
- Register Map842
- Register Map843
- Register Map844
- Register Map845
- Register Map846
- Register Map847
- Register Map848
- Register Map849
- Register Map850
- Register Map851
- Register Map852
- Register Map853
- Register Map854
- Register Map855
- Register Map856
- Register Map857
- Register Map858
- Register Map859
- Register Map860
- Register Map861
- Register Map862
- Register Map863
- Register Map864
- Register Map865
- Register Map866
- Register Map867
- Register Map868
- Register Map869
- Register Map870
- Register Map871
- Register Map872
- Register Map873
- Register Map874
- Register Map875
- Register Map876
- Register Map877
- Register Map878
- Register Map879
- Register Map880
- Register Map881
- Register Map882
- Register Map883
- Register Map884
- Register Map885
Register Map886
- Register Map887
- Register Map888
- Register Map889
- Register Map890
- Register Map891
- Register Map892
- Register Map893
- Register Map894
- Register Map895
- Register Map896
- Register Map897
- Register Map898
- Register Map899
- Register Map900
- Register Map901
- Register Map902
- Register Map903
- Register Map904
- Register Map905
- Register Map906
- Register Map907
- Register Map908
- Register Map909
- Register Map910
- Register Map911
- Register Map912
- B.1 Changes between Revisions 7 and 8914
- B.2 Changes between Revisions 5 and 7919
- B.3 Changes between Revisions 4 and 5921
- B.4 Changes between Revisions 2 and 4922
- B.5 Changes between Revisions 1 and 2931

Freescale Semiconductor MPC5604B - Page 154

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