MPC5604B/C Microcontroller Reference Manual, Rev. 8
176 Freescale Semiconductor
ME_<target mode>_MC registers, the MC_ME requests the FMPLL digital interface to start the phase
locking process and waits for the FMPLL to enter into the locked state. When the FMPLL enters the locked
state and starts providing a stable output clock, the S_FMPLL bit of ME_GS register is set.
8.4.3.10 Power Domain #2 Switch-On
On completion of the Main Voltage Regulator Switch-On, the MC_ME indicates a mode change to the
MC_PCU. The MC_PCU then determines whether a power-up sequence is required for power domain #2.
Only after the MC_PCU has executed all required power-ups does the MC_ME complete the mode
transition.
8.4.3.11 Pad Outputs-On
On completion of the Main Voltage Regulator Switch-On, if the PDO bit of the ME_<target mode>_MC
register is cleared, then
• all pad outputs are enabled to return to their previous state
• the I/O pads power sequence driver is switched on
8.4.3.12 Peripheral Clocks Enable
Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7,
ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks
for selected modules as required. This step is executed only after the Main Voltage Regulator Switch-On
process is completed.
Also if a mode change translates to a power up of one or more power domains, the MC_PCU indicates the
MC_ME after completing the power-up sequence upon which the MC_ME may assert the peripheral clock
enables of the peripherals residing in those power domains.
8.4.3.13 Processor and Memory Clock Enable
If the mode transition is from any of the low-power modes HALT or STOP to RUN0…3, the clocks to the
processor and system memories are enabled. The process of enabling these clocks is executed only after
the Flash Modules Switch-On process is completed.
8.4.3.14 Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT, STOP, or STANDBY to RUN0…3, the
MC_ME requests the processor to exit from its halted or stopped state. This step is executed only after the
Processor and Memory Clock Enable process is completed.
8.4.3.15 System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
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