Freescale Semiconductor MPC5604B - Page 228

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 217
10.3.1.3 Power Domain #2 Configuration Register (PCU_PCONF2)
This register defines for power domain #2 whether it is on or off in each device mode. The bit field
description is the same as in Table 10-3.
10.3.1.4 Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Address 0xC3FE_8008 Access: Supervisor read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
00
STBY0
00
STOP
0
HALT
RUN3 RUN2 RUN1 RUN0
DRUN
SAFE
TEST
RST
W
Reset0000010111111111
Figure 10-4. Power Domain #2 Configuration Register (PCU_PCONF2)
Address 0xC3FE_8040 Access: Supervisor read
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PD2 PD1 PD0
W
Reset0000000000000111
Figure 10-5. Power Domain Status Register (PCU_PSTAT)
Table 10-4. Power Domain Status Register (PCU_PSTAT) Field Descriptions
Field Description
PDn Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable