MPC5604B/C Microcontroller Reference Manual, Rev. 8
338 Freescale Semiconductor
19.5.3.7 Interrupt Filter Enable Register (IFER)
This register is used to enable a digital filter counter on the corresponding interrupt pads to filter out
glitches on the inputs.
19.5.3.8 Pad Configuration Registers (PCR0–PCR122)
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics
associated with I/O pads. Each PCR controls the characteristics of a single pad.
Please note that input and output peripheral muxing are separate.
• For output pads:
— Select the appropriate alternate function in Pad Config Register (PCR)
— OBE is not required for functions other than GPIO
• For INPUT pads:
— Select the feature location from PSMI register
— Set the IBE bit in the appropriate PCR
• For normal GPIO (not alternate function):
— Configure PCR
— Read from GPDI or write to GPDO
Offset:0x0030 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IFE[15:0]
1
1
IFE[15:0] in 144-pin LQFP and 208 MAPBGA packages; IFE[11:0] in 100-pin LQFP package.
W
Reset0000000000000000
Figure 19-8. Interrupt Filter Enable Register (IFER)
Table 19-9. IFER field descriptions
Field Description
IFE[x] Enable digital glitch filter on the interrupt pad input
0 Filter is disabled
1 Filter is enabled
See the IFMC field descriptions in Ta bl e 1 9-20 for details on how the filter works.
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