Freescale Semiconductor MPC5604B - Page 360

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 349
19.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all digital filter
counters in the SIUL.
Offset: 0x1000–0x103C) (16 registers) Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000
MAXCNTx
W
Reset0000000000000000
Figure 19-13. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
Table 19-20. IFMC field descriptions
Field Description
MAXCNTx Maximum Interrupt Filter Counter setting
Filter Period = T(CK)*MAXCNTx + n*T(CK)
Where (n can be 1 to 3)
MAXCNTx can be 0 to 15
T(CK): Prescaled Filter Clock Period, which is FIRC clock prescaled to IFCP value
T(FIRC): Basic Filter Clock Period: 62.5 ns (f
FIRC
= 16 MHz)
Offsets:0x1080 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000
IFCP
W
Reset0000000000000000
Figure 19-14. Interrupt Filter Clock Prescaler Register (IFCPR)