Freescale Semiconductor MPC5604B - Page 359

MPC5604B/C Microcontroller Reference Manual, Rev. 8
348 Freescale Semiconductor
For example in Table 19-18, the MPGPDO0 register contains field MASK0, which is the bitwise mask for
Port A and field MPPDO0, which contains data to be written to Port A.
• MPGPDO0[0] is the mask bit for Port A[0], MPGPDO0[1] is the mask bit for Port A[1] and so on,
through MPGPDO0[15], which is the mask bit for Port A[15]
• MPGPDO0[16] is the data bit mapped to Port A[0], MPGPDO0[17] is mapped to Port A[1] and so
on, through MPGPDO0[31], which is mapped to Port A[15].
CAUTION
Toggling several IOs at the same time can significantly increase the current
in a pad group. Caution must be taken to avoid exceeding maximum current
thresholds. Please see data sheet.
19.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
These registers are used to configure the filter counter associated with each digital glitch filter.
NOTE
For the pad transition to trigger an interrupt it must be steady for at least the
filter period.
Table 19-19. MPGPDO0..MPGPDO7 field descriptions
Field Description
MASK
x
[15:0]
Mask Field
Each bit corresponds to one data bit in the MPPDO
x
register at the same bit location.
0 Associated bit value in the MPPDO
x
field is ignored
1 Associated bit value in the MPPDO
x
field is written
MPPDO
x
[15:0]
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bitwise GPIO Pad Data Output
Registers (GPDO0_3–GPDO120_123).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[x][y] = PDO[(x*16)+y]