MPC5604B/C Microcontroller Reference Manual, Rev. 8
386 Freescale Semiconductor
AWUM Automatic Wake-Up Mode
This bit controls the behavior of the LINFlex hardware during Sleep mode.
0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR.
1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection. The
SLEEP bit of the LINCR is cleared by hardware whenever WUF bit in the LINSR is set.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
MBL LIN Master Break Length
This field indicates the Break length in Master mode (see Ta bl e 2 1-5).
Note: This field can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
BF Bypass filter
0 No interrupt if identifier does not match any filter.
1 An RX interrupt is generated on identifier not matching any filter.
Note:
• If no filter is activated, this bit is reserved and always reads 1.
• This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SFTM Self Test Mode
This bit controls the Self Test mode. For more details, see Section 21.6.2, Self Test mode.
0 Self Test mode disable.
1 Self Test mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LBKM Loop Back Mode
This bit controls the Loop Back mode. For more details see Section 21.6.1, Loop Back mode.
0 Loop Back mode disable.
1 Loop Back mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode
MME Master Mode Enable
0 Slave mode enable.
1 Master mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SBDT Slave Mode Break Detection Threshold
0 11-bit break.
1 10-bit break.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
RBLM Receive Buffer Locked Mode
0 Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming
message is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SLEEP Sleep Mode Request
This bit is set by software to request LINFlex to enter Sleep mode.
This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and
the WUF bit in LINSR are set (see Table 2 1-6).
INIT Initialization Request
The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset,
LINFlex enters Normal mode when clearing the INIT bit (see Table 21-6).
Table 21-3. LINCR1 field descriptions (continued)
Field Description
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