MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 385
21.7.1.1 LIN control register 1 (LINCR1)
0x0084 Identifier filter control register 14 (IFCR14) on page 408
0x0088 Identifier filter control register 15 (IFCR15) on page 408
0x008C–0x000F Reserved
1
LSB: Least significant byte
2
MSB: Most significant byte
Offset: 0x0000 Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CCD CFD LASE
AWUM
MBL BF
SFTM LBKM
MME
SBDT
RBLM
SLEEP
INIT
W
Reset0000000010000010
Figure 21-6. LIN control register 1 (LINCR1)
Table 21-3. LINCR1 field descriptions
Field Description
CCD Checksum calculation disable
This bit disables the checksum calculation (see Table 21-4).
0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only.
1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can
program this register to send a software-calculated CRC (provided CFD is 0).
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
CFD Checksum field disable
This bit disables the checksum field transmission (see Ta ble 21-4).
0 Checksum field is sent after the required number of data bytes is sent.
1 No checksum field is sent.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LASE LIN Slave Automatic Resynchronization Enable
0 Automatic resynchronization disable.
1 Automatic resynchronization enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
Table 21-2. LINFlex memory map (continued)
Address offset Register Location
To Next Page
Loading...
