MPC5604B/C Microcontroller Reference Manual, Rev. 8
388 Freescale Semiconductor
21.7.1.2 LIN interrupt enable register (LINIER)
Offset: 0x0004 Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SZIE OCIE BEIE CEIE HEIE
00
FEIE BOIE LSIE
WUIE
DBFIE DBEIE
DRIE DTIE HRIE
W
Reset0000000000000000
Figure 21-7. LIN interrupt enable register (LINIER)
Table 21-7. LINIER field descriptions
Field Description
SZIE Stuck at Zero Interrupt Enable
0 No interrupt when SZF bit in LINESR or UARTSR is set.
1 Interrupt generated when SZF bit in LINESR or UARTSR is set.
OCIE Output Compare Interrupt Enable
0 No interrupt when OCF bit in LINESR or UARTSR is set.
1 Interrupt generated when OCF bit in LINESR or UARTSR is set.
BEIE Bit Error Interrupt Enable
0 No interrupt when BEF bit in LINESR is set.
1 Interrupt generated when BEF bit in LINESR is set.
CEIE Checksum Error Interrupt Enable
0 No interrupt on Checksum error.
1 Interrupt generated when checksum error flag (CEF) in LINESR is set.
HEIE Header Error Interrupt Enable
0 No interrupt on Break Delimiter error, Synch Field error, Identifier field error.
1 Interrupt generated on Break Delimiter error, Synch Field error, Identifier field error.
FEIE Framing Error Interrupt Enable
0 No interrupt on Framing error.
1 Interrupt generated on Framing error.
BOIE Buffer Overrun Interrupt Enable
0 No interrupt on Buffer overrun.
1 Interrupt generated on Buffer overrun.
LSIE LIN State Interrupt Enable
0 No interrupt on LIN state change.
1 Interrupt generated on LIN state change.
This interrupt can be used for debugging purposes. It has no status flag but is reset when writing
‘1111’ into LINS[0:3] in the LINSR.
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