MPC5604B/C Microcontroller Reference Manual, Rev. 8
390 Freescale Semiconductor
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Table 21-8. LINSR field descriptions
Field Description
LINS LIN modes / normal mode states
0000: Sleep mode
LINFlex is in Sleep mode to save power consumption.
0001: Initialization mode
LINFlex is in Initialization mode.
Normal mode states
0010: Idle
This state is entered on several events:
• SLEEP bit and INIT bit in LINCR1 have been cleared by software,
• A falling edge has been received on RX pin and AWUM bit is set,
• The previous frame reception or transmission has been completed or aborted.
0011: Break
In Slave mode, a falling edge followed by a dominant state has been detected. Receiving Break.
Note: In Slave mode, in case of error new LIN state can be either Idle or Break depending on
last bit state. If last bit is dominant new LIN state is Break, otherwise Idle.
In Master mode, Break transmission ongoing.
0100: Break Delimiter
In Slave mode, a valid Break has been detected. See Section 21.7.1.1, LIN control register 1
(LINCR1) for break length configuration (10-bit or 11-bit). Waiting for a rising edge.
In Master mode, Break transmission has been completed. Break Delimiter transmission is
ongoing.
0101: Synch Field
In Slave mode, a valid Break Delimiter has been detected (recessive state for at least one bit
time). Receiving Synch Field.
In Master mode, Synch Field transmission is ongoing.
0110: Identifier Field
In Slave mode, a valid Synch Field has been received. Receiving Identifier Field.
In Master mode, identifier transmission is ongoing.
0111: Header reception/transmission completed
In Slave mode, a valid header has been received and identifier field is available in the BIDR.
In Master mode, header transmission is completed.
1000: Data reception/transmission
Response reception/transmission is ongoing.
1001: Checksum
Data reception/transmission completed. Checksum reception/transmission ongoing.
In UART mode, only the following states are flagged by the LIN state bits:
•Init
• Sleep
•Idle
• Data transmission/reception
RMB Release Message Buffer
0 Buffer is free.
1 Buffer ready to be read by software. This bit must be cleared by software after reading data
received in the buffer.
This bit is cleared by hardware in Initialization mode.
RBSY Receiver Busy Flag
0 Receiver is idle
1 Reception ongoing
Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit
is set. In this case, user cannot program LINCR2[DTRQ] = 1.
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