MPC5604B/C Microcontroller Reference Manual, Rev. 8
394 Freescale Semiconductor
21.7.1.6 UART mode status register (UARTSR)
RXEN Receiver Enable
0 Receiver disable.
1 Receiver enable.
This bit can be programmed only when the UART bit is set.
TXEN Transmitter Enable
0 Transmitter disable.
1 Transmitter enable.
This bit can be programmed only when the UART bit is set.
Note: Transmission starts when this bit is set and when writing DATA0 in the BDRL register.
OP Odd Parity
0 Sent parity is even.
1 Sent parity is odd.
This bit can be programmed in Initialization mode only when the UART bit is set.
PCE Parity Control Enable
0 Parity transmit/check disable.
1 Parity transmit/check enable.
This bit can be programmed in Initialization mode only when the UART bit is set.
WL Word Length in UART mode
0 7-bit data + parity bit.
1 8-bit data (or 9-bit if PCE is set).
This bit can be programmed in Initialization mode only when the UART bit is set.
UART UART mode enable
0LIN mode.
1UART mode.
This bit can be programmed in Initialization mode only.
Offset: 0x0014 Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SZF OCF PE3 PE2 PE1 PE0 RMB FEF BOF RPS WUF 0 0DRFDTFNF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset0000000000000000
Figure 21-11. UART mode status register (UARTSR)
Table 21-10. UARTCR field descriptions (continued)
Field Description
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