MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 439
CLK_SRC CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock
(driven by the FMPLL) or the crystal oscillator clock. The selected clock is the one fed to the
prescaler to generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit
should only be changed while the module is in Disable Mode. See Section 22.4.9.4, “Protocol timing
for more information.
1 = The CAN engine clock source is the bus clock
0 = The CAN engine clock source is the oscillator clock
Note: This clock selection feature may not be available in all MCUs. A particular MCU may not have
a FMPLL, in which case it would have only the oscillator clock, or it may use only the FMPLL
clock feeding the FlexCAN module. In these cases, this bit has no effect on the module
operation.
LPB Loop Back
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an
internal loop back that can be used for self test operation. The bit stream output of the transmitter
is fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output
goes to the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and
treats its own transmitted message as a message received from a remote node. In this mode,
FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating
an internal acknowledge bit to ensure proper reception of its own message. Both transmit and
receive interrupts are generated. This bit must be written in Freeze mode only.
1 = Loop Back enabled
0 = Loop Back disabled
TWRN_MSK Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the
Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read
as zero when WRN_EN is negated.
1 = Tx Warning Interrupt enabled
0 = Tx Warning Interrupt disabled
RWRN_MSK Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the
Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read
as zero when WRN_EN is negated.
1 = Rx Warning Interrupt enabled
0 = Rx Warning Interrupt disabled
SMP Sampling Mode
This bit defines the sampling mode of CAN bits at the Rx input. This bit must be written in Freeze
mode only.
1 = Three samples are used to determine the value of the received bit: the regular one (sample
point) and two preceding samples, a majority rule is used
0 = Just one sample is used to determine the bit value
Table 22-10. CTRL field descriptions (continued)
Field Description
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