Freescale Semiconductor MPC5604B - Page 512

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 501
Figure 23-14 shows conceptually how the SCK signal is generated.
Figure 23-14. Communications clock prescalers and scalers
23.6.4.1 Baud rate generator
The baud rate is the frequency of the serial communication clock (SCK_x). The system clock is divided
by a baud rate prescaler (defined by DSPIx_CTAR[PBR]) and baud rate scaler (defined by
DSPIx_CTAR[BR]) to produce SCK_x with the possibility of doubling the baud rate. The DBR, PBR, and
BR fields in the DSPIx_CTARs select the frequency of SCK_x using the following formula:
Table 23-25 shows an example of a computed baud rate.
23.6.4.2 CS to SCK delay (t
CSC
)
The CS_x to SCK_x delay is the length of time from assertion of the CS_x signal to the first SCK_x edge.
See Figure 23-16 for an illustration of the CS_x to SCK_x delay. The PCSSCK and CSSCK fields in the
DSPIx_CTARn registers select the CS_x to SCK_x delay, and the relationship is expressed by the
following formula:
Table 23-26 shows an example of the computed CS to SCK_x delay.
Table 23-25. Baud rate computation example
f
SYS
PBR Prescaler value BR Scaler value DBR value Baud rate
64 MHz 0b00 2 0b0000 2 0 16 Mbit/s
20 MHz 0b00 2 0b0000 2 1 10 Mbit/s
Table 23-26. CS to SCK delay computation example
PCSSCK Prescaler value CSSCK Scaler value f
SYS
CS to SCK delay
0b01 3 0b0100 32 64 MHz 1.5 µs
Prescaler
1
Scaler
1 + DBR
System Clock SCK_x
SCK baud rate
f
SYS
PBRPrescalerValue
----------------------------------------------------------
1DBR+
BRScalerValue
--------------------------------------------¥=
t
CSC
=
f
SYS
CSSCK

PCSSCK
1
