MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 655
If Stall/Abort-While-Write is enabled and an erase operation is started on one sector while fetching code
from another then the following sequence is executed:
• CPU is stalled when flash is unavailable
• PEG flag set (stall case) or reset (abort case)
• Interrupt triggered if enabled
If Stall/Abort-While-Write is used then application software should ignore the setting of the RWE flag.
The RWE flag should be cleared after each HV operation.
If Stall/Abort-While-Write is not used the application software should handle RWE error. See
Section 27.8.10, Read-while-write functionality.
27.5.1.2 CFlash Low/Mid Address Space Block Locking Register (CFLASH_LML)
The CFlash Low/Mid Address Space Block Locking register provides a means to protect blocks from
being modified. These bits, along with bits in the CFLASH_SLL register, determine if the block is locked
from Program or Erase. An “OR” of CFLASH_LML and CFLASH_SLL determine the final lock status.
Offset: 0x0004 Access: Read/write
0123456789101112131415
R
LME0000000000
TSLK
00
MLK
W
Reset Defined by CFLASH_NVLML at CFlash Test Sector Address 0x403DE8. This location is user OTP (One
Time Programmable). The CFLASH_NVLML register influences only the R/W bits of the CFLASH_LML
register.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0000000000
LLK
W
Reset Defined by CFLASH_NVLML at CFlash Test Sector Address 0x403DE8. This location is user OTP (One
Time Programmable). The CFLASH_NVLML register influences only the R/W bits of the CFLASH_LML
register.
Figure 27-4. CFlash Low/Mid Address Space Block Locking Register (CFLASH_LML)
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