Freescale Semiconductor MPC5604B - Page 675

MPC5604B/C Microcontroller Reference Manual, Rev. 8
664 Freescale Semiconductor
SMK Secondary Mid address space block locK
These bits are used as an alternate means to lock the blocks of Mid Address Space from
Program and Erase.
SMK[1:0] are related to sectors B0F7-6, respectively.
A value of 1 in a bit of the SMK register signifies that the corresponding block is locked for
Program and Erase.
A value of 0 in a bit of the SMK register signifies that the corresponding block is available to
receive program and erase pulses.
The SMK register is not writable once an interlock write is completed until
CFLASH_MCR[DONE] is set at the completion of the requested operation. Likewise, the
SMK register is not writable if a high voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the SMK registers. The SMK
bits may be written as a register. Reset will cause the bits to go back to their TestFlash block
value. The default value of the SMK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SMK
bits will default to locked, and will not be writable. The reset value will always be 1
(independent of the TestFlash block), and register writes will have no effect.
SMK is not writable unless SLE is high.
0: Mid Address Space Block is unlocked and can be modified (also if CFLASH_LML[MLK] =
0).
1: Mid Address Space Block is locked and cannot be modified.
SLK Secondary Low address space block locK
These bits are used as an alternate means to lock the blocks of Low Address Space from
Program and Erase.
SLK[5:0] are related to sectors B0F5-0, respectively. SLK[15:6] are not used for this memory
cut.
A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for
Program and Erase.
A value of 0 in a bit of the SLK register signifies that the corresponding block is available to
receive program and erase pulses.
The SLK register is not writable once an interlock write is completed until
CFLASH_MCR[DONE] is set at the completion of the requested operation. Likewise, the
SLK register is not writable if a high voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK
bits may be written as a register. Reset will cause the bits to go back to their TestFlash block
value. The default value of the SLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SLK
bits will default to locked, and will not be writable. The reset value will always be 1
(independent of the TestFlash block), and register writes will have no effect.
Bits SLK[15:6] are read-only and locked at ‘1’.
SLK is not writable unless SLE is high.
0: Low Address Space Block is unlocked and can be modified (also if CFLASH_LML[LLK] =
0).
1: Low Address Space Block is locked and cannot be modified.
Table 27-17. CFLASH_NVSLL field descriptions (continued)
Field Description