MPC5604B/C Microcontroller Reference Manual, Rev. 8
710 Freescale Semiconductor
27.6.3.2.2 Margin read
Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance
the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin
vs ‘0’ (UT0[MRV] = ‘0’) or vs ‘1’ (UT0[MRV] = ‘1’). Locked sectors are ignored by MISR calculation
and ECC flagging. The results of the margin reads can be checked comparing checksum value in
UMISR0-4. Since Margin reads are done at voltages that differ than the normal read voltage, lifetime
expectancy of the flash memory macrocell is impacted by the execution of Margin reads. Doing Margin
reads repetitively results in degradation of the flash memory Array, and shorten expected lifetime
experienced at normal read levels. For these reasons the Margin Read usage is allowed only in Factory,
while it is forbidden to use it inside the User Application.
In any case the charge losses detected through the Margin Read cannot be considered failures of the device
and no Failure Analysis will be opened on them. The Margin Read Setup operation consists of the
following sequence of events:
1. Set UT0[UTE] by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate bit(s) in the LMS register.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will
occur.
3. Set T0.AIS bit for a sequential addressing only.
4. Change the value in the UT0[MRE] bit from 0 to 1.
5. Select the Margin level: UT0[MRV]=0 for 0’s margin, UT0[MRV]=1 for 1’s margin.
6. Write a logic 1 to the UT0[AIE] bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0[AID] bit goes high.
8. Compare UMISR0-4 content with the expected result.
9. Write a logic 0 to the UT0[AIE], UT0[MRE] and UT0[MRV] bits.
10. If more blocks are to be checked, return to step 2.
It is mandatory to leave UT0[AIS] at 1 and use the linear address sequence, the usage of the proprietary
sequence in Margin Read is forbidden.
During the execution of the Margin Read operation it is forbidden to modify the content of Block Select
(LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an unpredictable way.
The read accesses will be done with the addition of a proper number of Wait States to guarantee the
correctness of the result.
While UT0[AID] is low and UT0[AIE] is high, the User may clear AIE, resulting in a Array Integrity
Check abort.
UT0[AID] must be checked to know when the aborting command has completed.
Example 27-6. Margin read setup versus ‘1’s
UMISR0 = 0x00000000; /* Reset UMISR0 content */
UMISR1 = 0x00000000; /* Reset UMISR1 content */
UMISR2 = 0x00000000; /* Reset UMISR2 content */
UMISR3 = 0x00000000; /* Reset UMISR3 content */
To Next Page
