MPC5604B/C Microcontroller Reference Manual, Rev. 8
720 Freescale Semiconductor
Table 27-58. PFCR0 field descriptions
Field Description
BK0_APC Bank0 Address Pipelining Control
This field is used to control the number of cycles between flash memory array access requests. This
field must be set to a value appropriate to the operating frequency of the PFlash. The required
settings are documented in the device data sheet. Higher operating frequencies require non-zero
settings for this field for proper flash memory operation.
00000: Accesses may be initiated on consecutive (back-to-back) cycles
00001: Access requests require one additional hold cycle
00010: Access requests require two additional hold cycles
...
11110: Access requests require 30 additional hold cycles
11111: Access requests require 31 additional hold cycles
Note:
BK0_WWSC Bank0 Write Wait-State Control
This field is used to control the number of wait-states to be added to the flash memory array access
time for writes. This field must be set to a value appropriate to the operating frequency of the PFlash.
The required settings are documented in the device data sheet. Higher operating frequencies
require non-zero settings for this field for proper flash memory operation. This field is set to an
appropriate value by hardware reset.
00000: No additional wait-states are added
00001: One additional wait-state is added
00010: Two additional wait-states are added
...
11111: 31 additional wait-states are added
Note:
BK0_RWSC Bank0 Read Wait-State Control
This field is used to control the number of wait-states to be added to the flash memory array access
time for reads. This field must be set to a value corresponding to the operating frequency of the
PFlash and the actual read access time of the PFlash. The required settings are documented in the
device datasheet.
00000: No additional wait-states are added
00001: One additional wait-state is added
00010: Two additional wait-states are added
...
11111: 31 additional wait-states are added
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