MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 721
BK0_RWWC Bank0 Read-While-Write Control
This 3-bit field defines the controller response to flash memory reads while the array is busy with a
program (write) or erase operation.
0––: This state should be avoided. Setting to this state can cause unpredictable operation.
111: Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort + abort notification interrupt
110: Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort + abort notification interrupt
101: Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification interrupt
100: Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
B0_P0_BCFG Bank0, Port 0 Page Buffer Configuration
This field controls the configuration of the four page buffers in the PFlash controller. The buffers can
be organized as a “pool” of available resources, or with a fixed partition between instruction and data
buffers.
If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group
and the just-fetched entry then marked as most-recently-used. If the flash memory access is for the
next-sequential line, the buffer is not marked as most-recently-used until the given address
produces a buffer hit.
00: All four buffers are available for any flash memory access, that is, there is no partitioning of the
buffers based on the access type.
01: Reserved
10: The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11: The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and
buffer 3 for data accesses.
This field is set to 2b11 by hardware reset.
B0_P0_DPFE Bank0, Port 0 Data Prefetch Enable
This field enables or disables prefetching initiated by a data read access. This field is cleared by
hardware reset. Prefetching can be enabled/disabled on a per Master basis at PFAPR[MxPFD].
0: No prefetching is triggered by a data read access
1: If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access
B0_P0_IPFE Bank0, Port 0 Instruction Prefetch Enable
This field enables or disables prefetching initiated by an instruction fetch read access. This field is
set by hardware reset. Prefetching can be enabled/disabled on a per Master basis at
PFAPR[MxPFD].
0: No prefetching is triggered by an instruction fetch read access
1: If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch
read access
Table 27-58. PFCR0 field descriptions (continued)
Field Description
To Next Page
Loading...
