MPC5604B/C Microcontroller Reference Manual, Rev. 8
772 Freescale Semiconductor
31.4.2.7.2 ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last, properly-enabled memory event to be detected. ECC
interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection
and the combination of the two as defined by the following boolean equations:
ECSM_ECC1BIT_IRQ
= ECR[ER1BR] & ESR[R1BC]// ram, 1-bit correction
| ECR[EF1BR] & ESR[F1BC]// flash, 1-bit correction
ECSM_ECCRNCR_IRQ
= ECR[ERNCR] & ESR[RNCE]// ram, noncorrectable error
ECSM_ECCFNCR_IRQ
= ECR[EFNCR] & ESR[FNCE]// flash, noncorrectable error
ECSM_ECC2BIT_IRQ
= ECSM_ECCRNCR_IRQ// ram, noncorrectable error
| ECSM_ECCFNCR_IRQ// flash, noncorrectable error
ECSM_ECC_IRQ
= ECSM_ECC1BIT_IRQ // 1-bit correction
| ECSM_ECC2BIT_IRQ// noncorrectable error
where the combination of a properly-enabled category in the ECR and the detection of the corresponding
condition in the ESR produces the interrupt request.
The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another
properly-enabled ECC event occurs, the ECSM hardware automatically handles the ESR reporting,
clearing the previous data and loading the new state and thus guaranteeing that only a single flag is
asserted.
To maintain the coherent software view of the reported event, the following sequence in the ECSM error
interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents matches the original contents. If the two values
are different, go back to step 1 and repeat.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
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