MPC5604B/C Microcontroller Reference Manual, Rev. 8
778 Freescale Semiconductor
31.4.2.7.7 Platform Flash ECC Data Register (PFEDR)
The PFEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the PFEAR, PFEMR,
PFEAT and PFEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored.
SIZE AMBA-AHB HSIZE[2:0]
000 8-bit AMBA-AHB access
001 16-bit AMBA-AHB access
010 32-bit AMBA-AHB access
1xx Reserved
PROTECTION AMBA-AHB HPROT[3:0]
Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable, 1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
Offset: 0x5C Access: Read
0123456789101112131415
R FEDR[31:16]
W
Reset:––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEDR[15:0]
W
Reset:––––––––––––––––
Figure 31-13. Platform Flash ECC Data Register (PFEDR)
Table 31-14. PFEDR field descriptions
Field Description
FEDR Flash ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last, properly-enabled
flash ECC event. The register contains the data value taken directly from the data bus.
Table 31-13. PFEAT field descriptions (continued)
Field Description
To Next Page
Loading...
