MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 777
31.4.2.7.5 Platform Flash ECC Master Number Register (PFEMR)
The PFEMR is a 4-bit register for capturing the XBAR bus master number of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash causes the address, attributes and data associated with the access to be loaded into the PFEAR,
PFEMR, PFEAT and PFEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
.
31.4.2.7.6 Platform Flash ECC Attributes Register (PFEAT)
The PFEAT is an 8-bit register for capturing the XBAR bus master attributes of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash causes the address, attributes and data associated with the access to be loaded into the PFEAR,
PFEMR, PFEAT and PFEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Offset: 0x56 Access: Read
01234567
R0000 FEMR
W
Reset:0000––––
Figure 31-11. Platform Flash ECC Master Number Register (PFEMR)
Table 31-12. PFEMR field descriptions
Field Description
FEMR Flash ECC Master Number Register
This 4-bit register contains the XBAR bus master number of the faulting access of the last,
properly-enabled flash ECC event.
Offset: 0x57 Access: Read
01234567
R WRITE SIZE PROTECTION
W
Reset:––––––––
Figure 31-12. Platform Flash ECC Attributes Register (PFEAT)
Table 31-13. PFEAT field descriptions
Field Description
WRITE AMBA-AHB HWRITE
0 AMBA-AHB read access
1 AMBA-AHB write access
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