MPC5604B/C Microcontroller Reference Manual, Rev. 8
776 Freescale Semiconductor
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])
and EEGR[ERRBIT] equals 64, then no data inversion will be generated.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
31.4.2.7.4 Platform Flash ECC Address Register (PFEAR)
The PFEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes
the address, attributes and data associated with the access to be loaded into the PFEAR, PFEMR, PFEAT
and PFEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Offset: 0x50 Access: Read
0123456789101112131415
R FEAR[31:16]
W
Reset:––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEAR[15:0]
W
Reset:––––––––––––––––
Figure 31-10. Platform Flash ECC Address Register (PFEAR)
Table 31-11. PFEAR field descriptions
Field Description
FEAR Flash ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled flash ECC
event.
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