Freescale Semiconductor MPC5604B - Page 790

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 779
31.4.2.7.8 Platform RAM ECC Address Register (PREAR)
The PREAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM
causes the address, attributes and data associated with the access to be loaded into the PREAR, PRESR,
PREMR, PREAT and PREDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
31.4.2.7.9 Platform RAM ECC Syndrome Register (PRESR)
The PRESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event
in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
SRAM causes the address, attributes and data associated with the access to be loaded into the PREAR,
PRESR, PREMR, PREAT and PREDR registers, and the appropriate flag (R1BC or RNCE) in the ECC
Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Offset: 0x60 Access: Read
0123456789101112131415
R REAR[31:16]
W
Reset:––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REAR[15:0]
W
Reset:––––––––––––––––
Figure 31-14. Platform RAM ECC Address Register (PREAR)
Table 31-15. PREAR field descriptions
Field Description
REAR SRAM ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled SRAM ECC
event.
Offset: 0x65 Access: Read
01234567
R RESR
W
Reset:––––––––
Figure 31-15. Platform RAM ECC Syndrome Register (PRESR)