MPC5604B/C Microcontroller Reference Manual, Rev. 8
918 Freescale Semiconductor
Enhanced Modular IO
Subsystem
Organizational, editorial and formatting changes, including changing ‘$’ to ‘0x’ throughout
Section 27.1.2, “Features of the eMIOS module”: Removed “identical” from first bullet in list
Removed “identical’ from first bullet in features list
Channel configuration:
– Modified eMIOS block numbering—Was eMIOS_A and eMIOS_B, is eMIOS_0 and
eMIOS_1
– Corrected position of horizontal arrow between Counter Bus_B and Ch1 in eMIOS_0
– Added GPIO to diagram key
Updated Section 27.1.5.1, “Channel mode selection”
Section 27.3, “Memory map and register description”: Harmonized register naming and
added location columns to memory map tables
eMIOS Module Configuration Register (EMIOSMCR): Changed reset value of MDIS to ‘0’
EMIOSMCR field descriptions: Corrected table title
EMIOSOUDIS register field descriptions: Replaced OU31:OU0 with OU27:OU0
Updated Section 27.3.2.8, “eMIOS UC Control Register (EMIOSC[n])”
UC BSL bits: Added “Channels 24 to 27: counter bus[E]” to selected bus for field value ‘01’
EMIOSS[n] register field descriptions: Updated FLAG field description
Section 27.4, “Functional description”: Changed the number of channel types; was three,
is five
Updated Section 27.5.2.2, “Coherent accesses”
Unified Channel block diagram:
– Changed ips_wda to ips_wdata[0:31]
– Changed uc_rd_d to uc_rd_data[0:31]
– Changed ips_add to ips_addr[27:29]
Analog-to-Digital
Converter
Section 25.1.4, “Device-specific features”:
– Replaced MA[0:2] with MA[2:0]
– Removed 1.2 V from presampling options
Updated ADC implementation diagram
Updated Section 25.2, “Introduction”
Section 25.3.1.1, “Normal conversion”: Minor editorial change
Section 25.3.1.2, “Start of normal conversion”: Minor editorial change
Updated second paragraph in Section 25.3.2, “Analog clock generator and conversion
timings”
Updated Section 25.3.3, “ADC sampling and conversion timing”
Updated Section 25.3.5.2, “Presampling channel enable signals”
Updated Presampling voltage selection based on PREVALx fields
Updated Section 25.3.8, “Interrupts”
Main Configuration Register (MCR) field descriptions: Updated description for field
OWREN
Main Status Register (MSR) field descriptions: Updated values for ADCSTATUS[0:2] (and
removed stand-alone description table for this field)
Watchdog Threshold Interrupt Status Register (WTISR) field descriptions: Changed
“corresponds to the interrupt generated “ to “corresponds to the status flag generated” in
both bit descriptions
Presampling Control Register (PSCR) field descriptions: Updated descriptions for PREVAL
fields
Section 25.4.12, “Conversion timing registers CTR[01..12]”: Restored OFFSHIFT field
Channel Data Register (CDR[0..95]) field descriptions:
– Updated description for field OVERW
– Added value ‘11’ to field RESULT[0:1]
Table B-4. Changes between revisions 2 and 4 (continued)
Chapter Description
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