Freescale Semiconductor MPC5604B - Page 99

MPC5604B/C Microcontroller Reference Manual, Rev. 8
88 Freescale Semiconductor
Offset: 0x0C Access: Read/write
0123456789101112131415
R0000000000000000
W PWD_HI[31:16]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PWD_HI[15:0]
Reset0000000000000000
Figure 5-17. Password Comparison Register High Word (SSCM_PWCMPH)
Offset: 0x10 Access: Read/write
0123456789101112131415
R0000000000000000
W PWD_LO[31:16]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PWD_LO[15:0]
Reset0000000000000000
Figure 5-18. Password Comparison Register Low Word (SSCM_PWCMPL)
Table 5-20. Password Comparison Register field descriptions
Field Description
PWD_HI Upper 32 bits of the password
PWD_LO Lower 32 bits of the password
Table 5-21. SSCM_PWCMPH/L allowed register accesses
Access type 8-bit 16-bit 32-bit
1
1
All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).
Read Allowed Allowed Allowed
Write Not allowed Not allowed Allowed