Intel ARCHITECTURE IA-32 User Manual

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Sign Extension to Full 64-Bits........................................................................................... 8-3
Alternate Coding Rules for 64-Bit Mode.................................................................................. 8-4
Use 64-Bit Registers Instead of Two 32-Bit Registers for 64-Bit Arithmetic..................... 8-4
Use 32-Bit Versions of CVTSI2SS and CVTSI2SD When Possible................................. 8-6
Using Software Prefetch................................................................................................... 8-6
Chapter 9 Power Optimization for Mobile Usages
Overview................................................................................................................................. 9-1
Mobile Usage Scenarios......................................................................................................... 9-2
ACPI C-States......................................................................................................................... 9-4
Processor-Specific C4 and Deep C4 States..................................................................... 9-6
Guidelines for Extending Battery Life...................................................................................... 9-7
Adjust Performance to Meet Quality of Features ............................................................. 9-8
Reducing Amount of Work................................................................................................ 9-9
Platform-Level Optimizations.......................................................................................... 9-10
Handling Sleep State Transitions ................................................................................... 9-11
Using Enhanced Intel SpeedStep
®
Technology ............................................................. 9-12
Enabling Intel
®
Enhanced Deeper Sleep ....................................................................... 9-14
Multi-Core Considerations.............................................................................................. 9-15
Enhanced Intel SpeedStep
®
Technology.................................................................. 9-15
Thread Migration Considerations.............................................................................. 9-16
Multi-core Considerations for C-States..................................................................... 9-17
Appendix AApplication Performance Tools
Intel
®
Compilers..................................................................................................................... A-2
Code Optimization Options ............................................................................................. A-3
Targeting a Processor (-Gn) ...................................................................................... A-3
Automatic Processor Dispatch Support (-Qx[extensions] and -Qax[extensions])...... A-4
Vectorizer Switch Options ............................................................................................... A-5
Loop Unrolling............................................................................................................ A-5
Multithreading with OpenMP*.................................................................................... A-6
Inline Expansion of Library Functions (-Oi, -Oi-) ............................................................. A-6
Floating-point Arithmetic Precision (-Op, -Op-, -Qprec, -Qprec_div, -Qpc,
-Qlong_double)............................................................................................................ A-6
Rounding Control Option (-Qrcd) .................................................................................... A-6
Interprocedural and Profile-Guided Optimizations .......................................................... A-7
Interprocedural Optimization (IPO)............................................................................ A-7
Profile-Guided Optimization (PGO) ........................................................................... A-7
Intel
®
VTune™ Performance Analyzer................................................................................... A-8
Sampling ......................................................................................................................... A-9

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)