Intel ARCHITECTURE IA-32 User Manual

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Time-based Sampling................................................................................................ A-9
Event-based Sampling............................................................................................. A-10
Workload Characterization ...................................................................................... A-11
Call Graph ..................................................................................................................... A-13
Counter Monitor............................................................................................................. A-14
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Tuning Assistant.................................................................................................. A-14
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Performance Libraries................................................................................................ A-14
Benefits Summary ......................................................................................................... A-15
Optimizations with the Intel
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Performance Libraries.................................................... A-16
Enhanced Debugger (EDB) ................................................................................................. A-17
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Threading Tools.......................................................................................................... A-17
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Thread Checker................................................................................................... A-17
Thread Profiler............................................................................................................... A-19
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Software College........................................................................................................ A-20
Appendix BUsing Performance Monitoring Events
Pentium 4 Processor Performance Metrics............................................................................ B-1
Pentium 4 Processor-Specific Terminology............................................................................ B-2
Bogus, Non-bogus, Retire............................................................................................... B-2
Bus Ratio......................................................................................................................... B-2
Replay ............................................................................................................................. B-3
Assist............................................................................................................................... B-3
Tagging............................................................................................................................ B-3
Counting Clocks..................................................................................................................... B-4
Non-Halted Clockticks..................................................................................................... B-5
Non-Sleep Clockticks ...................................................................................................... B-6
Time Stamp Counter........................................................................................................ B-7
Microarchitecture Notes......................................................................................................... B-8
Trace Cache Events........................................................................................................ B-8
Bus and Memory Metrics................................................................................................. B-8
Reads due to program loads ................................................................................... B-11
Reads due to program writes (RFOs)...................................................................... B-11
Writebacks (dirty evictions)...................................................................................... B-12
Usage Notes for Specific Metrics .................................................................................. B-13
Usage Notes on Bus Activities ...................................................................................... B-15
Metrics Descriptions and Categories ................................................................................... B-16
Performance Metrics and Tagging Mechanisms.................................................................. B-46
Tags for replay_event .................................................................................................... B-46
Tags for front_end_event............................................................................................... B-48
Tags for execution_event .............................................................................................. B-48

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)