Intel ARCHITECTURE IA-32 - Page 14

xiv
Using Performance Metrics with Hyper-Threading Technology ........................................... B-50
Using Performance Events of Intel Core Solo and Intel Core Duo processors.................... B-56
Understanding the Results in a Performance Counter.................................................. B-56
Ratio Interpretation........................................................................................................ B-57
Notes on Selected Events............................................................................................. B-58
Appendix CIA-32 Instruction Latency and Throughput
Overview................................................................................................................................ C-2
Definitions .............................................................................................................................. C-4
Latency and Throughput ........................................................................................................ C-4
Latency and Throughput with Register Operands.......................................................... C-6
Table Footnotes....................................................................................................... C-19
Latency and Throughput with Memory Operands ......................................................... C-20
Appendix DStack Alignment
Stack Frames ......................................................................................................................... D-1
Aligned esp-Based Stack Frames ................................................................................... D-4
Aligned ebp-Based Stack Frames................................................................................... D-6
Stack Frame Optimizations.............................................................................................. D-9
Inlined Assembly and ebx.................................................................................................... D-10
Appendix EMathematics of Prefetch Scheduling Distance
Simplified Equation ................................................................................................................ E-1
Mathematical Model for PSD ................................................................................................. E-2
No Preloading or Prefetch............................................................................................... E-6
Compute Bound (Case:Tc >= T
l
+ T
b
) ............................................................................. E-7
Compute Bound (Case: Tl + Tb > Tc > Tb) ..................................................................... E-8
Memory Throughput Bound (Case: Tb >= Tc)............................................................... E-10
Example ........................................................................................................................ E-11
Index