Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-56
PackageID[ProcessorNUM] = PACKAGE_ID;
CoreID[ProcessorNum] = CORE_ID;
SmtID[ProcessorNum] = SMT_ID;
CacheID[ProcessorNUM] = CACHE_ID;
// Only the target cache is stored in this example
ProcessorNum++;
}
ThreadAffinityMask <<= 1;
}
NumStartedLPs = ProcessorNum;
CacheIDBucket is an array of unique Cache_ID values. Allocate an array
of NumStartedLPs count of entries in this array for the target cache level.
CacheProcessorMask is a corresponding array of the bit mask of logical
processors sharing the same target level cache, these are logical
processors with the same Cache_ID.
The algorithm below assumes there is symmetry across the modular
boundary of target cache topology if more than one socket is populated
in an MP system, and only the topology of the target cache level is discovered.
Topology of other cache level can be determined in a similar manner.
// Bucket Cache IDs and compute processor mask for the target cache of every package.
CacheNum = 1;
CacheIDBucket[0] = CacheID[0];
ProcessorMask = 1;
CacheProcessorMask[0] = ProcessorMask;
Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors
Sharing the Same Cache (Contd.)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)