Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-57
For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) {
ProcessorMask << = 1;
For (i = 0; i < CacheNum; i++) {
// We may be comparing bit-fields of logical processors
// residing in a different modular boundary of the cache
// topology, the code below assume symmetry across this
// modular boundary.
If (CacheID[ProcessorNum] == CacheIDBucket[i]) {
CacheProcessorMask[i] |= ProcessorMask;
Break; //Found in existing bucket,skip to next iteration.
}
}
if (i == CacheNum) {
// Cache_ID did not match any bucket, start new bucket.
CacheIDBucket[i] = CacheID[ProcessorNum];
CacheProcessorMask[i] = ProcessorMask;
CacheNum++;
}
}
// CacheNum has the number of distinct modules which contain
// sibling logical processor sharing the target Cache.
// CacheProcessorMask[] array has the mask representing those logical
// processors sharing the same target level cache.
Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors
Sharing the Same Cache (Contd.)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)