Intel ARCHITECTURE IA-32 - Page 403

Multi-Core and Hyper-Threading Technology 7
7-57
For (ProcessorNum = 1; ProcessorNum < NumStartedLPs; ProcessorNum++) {
ProcessorMask << = 1;
For (i = 0; i < CacheNum; i++) {
// We may be comparing bit-fields of logical processors
// residing in a different modular boundary of the cache
// topology, the code below assume symmetry across this
// modular boundary.
If (CacheID[ProcessorNum] == CacheIDBucket[i]) {
CacheProcessorMask[i] |= ProcessorMask;
Break; //Found in existing bucket,skip to next iteration.
}
}
if (i == CacheNum) {
// Cache_ID did not match any bucket, start new bucket.
CacheIDBucket[i] = CacheID[ProcessorNum];
CacheProcessorMask[i] = ProcessorMask;
CacheNum++;
}
}
// CacheNum has the number of distinct modules which contain
// sibling logical processor sharing the target Cache.
// CacheProcessorMask[] array has the mask representing those logical
// processors sharing the same target level cache.
Example 7-13 Discovering the Affinity Masks for Sibling Logical Processors
Sharing the Same Cache (Contd.)