Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-58
Optimization of Other Shared Resources
Resource optimization in multi-threaded application depends on the
cache topology and execution resources associated within the hierarchy
of processor topology. Processor topology and an algorithm for software
to identify the processor topology are discussed in the IA-32 Intel®
Architecture Software Developer’s Manual, Volume 3A.
Typically the bus system is shared by multiple agents at the SMT level
and at the processor core level of the processor topology. Thus
multi-threaded application design should start with an approach to
manage the bus bandwidth available to multiple processor agents
sharing the same bus link in an equitable manner. This can be done by
improving the data locality of an individual application thread or
allowing two threads to take advantage of a shared second-level cache
(where such shared cache topology is available).
In general, optimizing the building blocks of a multi-threaded
application can start from an individual thread. The guidelines discussed
in Chapters 2 through 6 largely apply to multi-threaded optimization.
Tuning Suggestion 3. (H Impact, H Generality) Optimize single threaded
code to maximize execution throughput first.
At the SMT level, Hyper-Threading Technology typically can provide
two logical processors sharing execution resources within a processor
core. To help multithreaded applications utilize shared execution
resources effectively, the rest of this section describes guidelines to deal
with common situations as well as those limited situations where
execution resource utilization between threads may impact overall
performance.
Most applications only use about 20-30% of peak execution resources
when running in a single-threaded environment. A useful indicator that
relates to this is by measuring the execution throughput at the retirement
stage (See “Workload Characterization” in Appendix A). In a processor
that supports Hyper-Threading Technology, execution throughput

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)