Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-24
Trace Cache
Misses
The number of times
that significant
delays occurred in
order to decode
instructions and build
a trace because of a
TC miss.
BPU_fetch_request TCMISS
TC to ROM
Transfers
Twice the number of
times that the ROM
microcode is
accessed to decode
complex IA-32
instructions instead
of building|delivering
traces. (Divide the
count by 2 to get the
number of
occurrence.)
tc_ms_xfer CISC
Speculative
TC-Built Uops
The number of
speculative uops
originating when the
TC is in build mode.
uop_queue_writes FROM_TC_BUILD
Speculative
TC-Delivered
Uops
The number of
speculative uops
originating when the
TC is in deliver
mode.
uop_queue_writes FROM_TC_DELIVER
Speculative
Microcode
Uops
The number of
speculative uops
originating from the
microcode ROM (Not
all uops of an
instruction from the
microcode ROM will
be included).
uop_queue_writes FROM_ROM
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)