Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-25
Memory Metrics
Page Walk
DTLB All
Misses
The number of page
walk requests due to
DTLB misses from
either load or store.
page_walk_type DTMISS
1
st
-Level Cache
Load Misses
Retired
The number of
retired μops that
experienced
1
st
-Level cache load
misses. This stat is
often used in a
per-instruction ratio.
Replay_event; set the
following replay tag:
1stL_cache_load
_miss_retired
NBOGUS
2
nd
-Level
Cache Load
Misses Retired
The number of
retired load μops that
experienced
2
nd
-Level cache
misses. This stat is
known to undercount
when loads are
spaced apart.
Replay_event; set the
following replay tag:
2ndL_cache_load_
miss_retired
NBOGUS
DTLB Load
Misses Retired
The number of
retired load μops that
experienced DTLB
misses.
Replay_event; set the
following replay tag:
DTLB_load_miss_
retired
NBOGUS
DTLB Store
Misses Retired
The number of
retired store μops
that experienced
DTLB misses.
Replay_event; set the
following replay tag:
DTLB_store_miss_
retired
NBOGUS
DTLB Load and
Store Misses
Retired
The number of
retired load or μops
that experienced
DTLB misses.
Replay_event; set the
following replay tag:
DTLB_all_miss_
retired
NBOGUS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)