Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-29
3rd-Level
Cache Reads
Hit Modified
The number of
3rd-level cache read
references (loads
and RFOs) that hit
the cache line in
modified state.
Beware of granularity
differences.
BSQ_cache_reference RD_3rdL_HITM
3rd-Level
Cache Reads
Hit Exclusive
The number of
3rd-level cache read
references (loads
and RFOs) that hit
the cache line in
exclusive state.
Beware of granularity
differences.
BSQ_cache_reference RD_3rdL_HITE
MOB Load
Replays Retired
The number of
retired load μops that
experienced replays
related to the MOB.
Replay_event; set the
following replay tag:
MOB_load_replay_
retired
NBOGUS
Loads Retired The number of
retired load
operations that were
tagged at the front
end.
Front_end_event; set
the following front end
tag: Memory_loads
NBOGUS
Stores Retired The number of
retired stored
operations that were
tagged at the front
end. This stat is often
used in a
per-instruction ratio.
Front_end_event; set
the following front end
tag: Memory_stores
NBOGUS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)