Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-30
All WCB
Evictions
The number of times
a WC buffer eviction
occurred due to any
causes (This can be
used to distinguish
64K aliasing cases
that contribute more
significantly to
performance penalty,
e.g., stores that are
64K aliased. A high
count of this metric
when there is no
significant
contribution due to
write combining
buffer full condition
may indicate such a
situation.)
WC_buffer WCB_EVICTS
WCB Full
Evictions
The number of times
a WC buffer eviction
occurred when all of
the WC buffers are
already allocated.
WC_buffer WCB_FULL_EVICT
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)