Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-40
Reads
Non-prefetch
Full (BSQ)
The number of read
(excludes RFOs and
HW|SW prefetches)
transactions to
WB-type memory.
Beware of granularity
issues with this
event.
BSQ_allocation 1. REQ_LEN0|
REQ_LEN1|
MEM_TYPE1|
MEM_TYPE2|
REQ_CACHE_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
Reads
Invalidate Full-
RFO (BSQ)
The number of read
invalidate (RFO)
transactions to
WB-type memory.
BSQ_allocation 1. REQ_TYPE0|
REQ_LEN0|
REQ_LEN1|
MEM_TYPE1|
MEM_TYPE2|
REQ_CACHE_TYPE|
REQ_ORD_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
UC Reads
Chunk (BSQ)
The number of
8-byte aligned UC
read transactions.
User note: Read
requests associated
with 16 byte
operands may
under-count.
BSQ_allocation 1. REQ_LEN0|
REQ_ORD_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
UC Reads
Chunk Split
(BSQ)
The number of UC
read transactions
that span an 8-byte
boundary. User note:
Read requests may
under-count if the
data chunk straddles
64-byte boundary.
BSQ_allocation 1. REQ_LEN0|
REQ_SPLIT_TYPE|
REQ_ORD_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)