Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-39
Write WC Full
(BSQ)
The number of write
(but neither
writeback nor RFO)
transactions to
WC-type memory.
BSQ_allocation 1. REQ_TYPE1|
REQ_LEN0|
REQ_LEN1|MEM_
TYPE0|REQ_DEM_
TYPE
2. Enable edge
filtering
6
in
the CCCR.
Write WC
Partial (BSQ)
The number of
partial write
transactions to
WC-type memory.
User note: This event
may undercount WC
partials that originate
from DWord
operands.
BSQ_allocation 1. REQ_TYPE1|
REQ_LEN0|
MEM_TYPE0|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
Writes WB Full
(BSQ)
The number of
writeback (evicted
from cache)
transactions to
WB-type memory.
Note: These
writebacks may not
have a
corresponding FSB
IOQ transaction if
3rd level cache is
present.
BSQ_allocation 1. REQ_TYPE0|
REQ_TYPE1|
REQ_LEN0|
REQ_LEN1|
MEM_TYPE1|
MEM_TYPE2|
REQ_CACHE_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)