Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-42
WB Writes Full
Underway
(BSQ)
8
This is an accrued
sum of the durations
of writeback (evicted
from cache)
transactions to
WB-type memory.
Divide by Writes WB
Full (BSQ) to
estimate average
request latency. User
note: Beware of
effects of writebacks
from 2nd-level cache
that are quickly
satisfied from the
3rd-level cache (if
present).
BSQ_active_entries 1. REQ_TYPE0|
REQ_TYPE1|
REQ_LEN0|
REQ_LEN1|
MEM_TYPE1|
MEM_TYPE2|
REQ_CACHE_TYPE|
REQ_DEM_TYPE
UC Reads
Chunk
Underway
(BSQ)
8
This is an accrued
sum of the durations
of UC read
transactions. Divide
by UC Reads Chunk
(BSQ) to estimate
average request
latency. User note:
Estimated latency
may be affected by
undercount in
allocated entries.
BSQ_active_entries 1. REQ_LEN0|
REQ_ORD_TYPE|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)