Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-43
Write WC Partial
Underway
(BSQ)
8
This is an accrued
sum of the durations
of partial write
transactions to
WC-type memory.
Divide by Write WC
Partial (BSQ) to
estimate average
request latency. User
note: Allocated
entries of WC
partials that originate
from DWord
operands are not
included.
BSQ_active_entries 1. REQ_TYPE1|
REQ_LEN0|
MEM_TYPE0|
REQ_DEM_TYPE
2. Enable edge
filtering
6
in
the CCCR.
Characterization Metrics
x87 Input
Assists
The number of
occurrences of x87
input operands
needing assistance
to handle an
exception condition.
This stat is often
used in a
per-instruction ratio.
X87_assists PREA
x87 Output
Assists
The number of
occurrences of x87
operations needing
assistance to handle
an exception
condition.
X87_assists POAO, POAU
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)