Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-44
SSE Input
Assists
The number of
occurrences of
SSE/SSE2
floating-point
operations needing
assistance to handle
an exception
condition. The
number of
occurrences includes
speculative counts.
SSE_input_assist ALL
Packed SP
Retired
3
Non-bogus packed
single-precision
instructions retired.
Execution_event; set
this execution tag:
Packed_SP_retired
NONBOGUS0
Packed DP
Retired
3
Non-bogus packed
double-precision
instructions retired.
Execution_event; set
this execution tag:
Packed_DP_retired
NONBOGUS0
Scalar SP
Retired
3
Non-bogus scalar
single-precision
instructions retired.
Execution_event; set
this execution tag:
Scalar_SP_retired
NONBOGUS0
Scalar DP
Retired
3
Non-bogus scalar
double-precision
instructions retired.
Execution_event; set
this execution tag:
Scalar_DP_retired
NONBOGUS0
64-bit MMX
Instructions
Retired
3
Non-bogus 64-bit
integer SIMD
instruction (MMX
instructions) retired.
Execution_event; set the
following execution tag:
64_bit_MMX_retired
NONBOGUS0
128-bit MMX
Instructions
Retired
3
Non-bogus 128-bit
integer SIMD
instructions retired.
Execution_event; set
this execution tag:
128_bit_MMX_
retired
NONBOGUS0
X87 Retired
4
Non-bogus x87
floating-point
instructions retired.
Execution_event; set
this execution tag:
X87_FP_retired
NONBOGUS0
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)