Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-45
1. A memory reference causing 64K aliasing conflict can be counted more than once in this stat. The resulting
performance penalty can vary from unnoticeable to considerable. Some implementations of the Pentium 4 processor
family can incur significant penalties from loads that alias to preceding stores.
2. Currently, bugs in this event can cause both overcounting and undercounting by as much as a factor of 2.
3. Most MMX technology instructions, Streaming SIMD Extensions and Streaming SIMD Extensions 2 decode into a
single
μop. There are some instructions that decode into several μops; in these limited cases, the metrics count the
number of
μops that are actually tagged.
Stalled Cycles
of Store Buffer
Resources
(non-standard
5
)
The duration of stalls
due to lack of store
buffers.
Resource_stall SBFULL
Stalls of Store
Buffer
Resources
(non-standard
5
)
The number of
allocation stalls due
to lack of store
buffers.
Resource_stall SBFULL
(Also Set the
following CCCR bits:
Compare=1;
Edge=1;
Threshold=0)
Machine Clear Metrics
Machine Clear
Count
The number of
cycles that the entire
pipeline of the
machine is cleared
for all causes.
Machine_clear CLEAR
(Also Set the
following CCCR bits:
Compare=1;
Edge=1;
Threshold=0)
Memory Order
Machine Clear
The number of times
that the entire
pipeline of the
machine is cleared
due to memory-
ordering issues.
Machine_clear MOCLEAR
Self-modifying
Code Clear
The number of times
the entire pipeline of
the machine is
cleared due to
self-modifying code
issues.
Machine_clear SMCCLEAR
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)