Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
C-10
COMISD xmm, xmm 7 6 1 2 2 1 FP_ADD,
FP_MISC
CVTDQ2PD xmm, xmm 8 8 4+1 3 3 4 FP_ADD,
MMX_SHFT
CVTPD2PI mm, xmm 12 11 5 3 3 3 FP_ADD,
MMX_SHFT,
MMX_ALU
CVTPD2DQ xmm, xmm 10 9 5 2 2 3 FP_ADD,
MMX_SHFT
CVTPD2PS
3
xmm, xmm 11 10 2 2 FP_ADD,
MMX_SHFT
CVTPI2PD xmm, mm 12 11 4+1 2 4 4 FP_ADD,
MMX_SHFT,
MMX_ALU
CVTPS2PD
3
xmm, xmm 3 2 2+1 2 3 FP_ADD,
MMX_SHFT,
MMX_ALU
CVTSD2SI r32, xmm 9 8 2 2 FP_ADD,
FP_MISC
CVTSD2SS
3
xmm, xmm 17 16 4 2 4 1 FP_ADD,
MMX_SHFT
CVTSI2SD
3
xmm, r32 16 15 4 2 3 1 FP_ADD,
MMX_SHFT,
MMX_MISC
CVTSS2SD
3
xmm, xmm 98 2 22 2
CVTTPD2PI mm, xmm 12 11 5 3 3 3 FP_ADD,
MMX_SHFT,
MMX_ALU
CVTTPD2DQ xmm, xmm 10 9 2 2 FP_ADD,
MMX_SHFT
CVTTSD2SI r32, xmm 8 8 2 2 FP_ADD,
FP_MISC
continued
Table C-3 Streaming SIMD Extension 2 Double-precision Floating-point
Instructions (continued)
Instruction Latency
1
Throughput
Execution
Unit
2

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)