Intel ARCHITECTURE IA-32 User Manual

IA-32 Instruction Latency and Throughput C
C-11
DIVPD xmm, xmm 70 69 32+31 70 69 62 FP_DIV
DIVSD xmm, xmm 39 38 32 39 38 31 FP_DIV
MAXPD xmm, xmm 5 4 4 2 2 2 FP_ADD
MAXSD xmm, xmm 5 4 3 2 2 1 FP_ADD
MINPD xmm, xmm 5 4 4 2 2 2 FP_ADD
MINSD xmm, xmm 5 4 3 2 2 1 FP_ADD
MOVAPD xmm, xmm 6 6 1 1 FP_MOVE
MOVMSKPD r32, xmm 6 6 2 2 FP_MISC
MOVSD xmm, xmm 6 6 2 2 MMX_SHFT
MOVUPD xmm, xmm 6 6 1 1 FP_MOVE
MULPD xmm, xmm 7 6 2 2 FP_MUL
MULSD xmm, xmm 7 6 2 2 FP_MUL
ORPD
3
xmm, xmm 4 4 2 2 MMX_ALU
SHUFPD
3
xmm, xmm,
imm8
6 6 2 2 MMX_SHFT
SQRTPD xmm, xmm 70 69 58+57 70 69 114 FP_DIV
SQRTSD xmm, xmm 39 38 58 39 38 57 FP_DIV
SUBPD xmm, xmm 5 4 4 2 2 2 FP_ADD
SUBSD xmm, xmm 5 4 3 2 2 1 FP_ADD
UCOMISD xmm, xmm 7 6 1 2 2 1 FP_ADD,
FP_MISC
UNPCKHPD
3
xmm, xmm 6 6 1 2 2 1 MMX_SHFT
UNPCKLPD
3
xmm, xmm 4 4 1 2 2 1 MMX_SHFT
XORPD
3
xmm, xmm 4 4 1 2 2 1 MMX_ALU
See “Table Footnotes”
Table C-3 Streaming SIMD Extension 2 Double-precision Floating-point
Instructions (continued)
Instruction Latency
1
Throughput
Execution
Unit
2

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)