MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 145
Table 8-4. Global Status Register (ME_GS) Field Descriptions
Field Description
S_CURREN
T_MODE
Current device mode status
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT
1001 reserved
1010 STOP
1011 reserved
1100 reserved
1101 STANDBY
1110 reserved
1111 reserved
S_MTRANS Mode transition status
0 Mode transition process is not active
1 Mode transition is ongoing
S_DC Device current consumption status
0 Device consumption is low enough to allow powering down of main voltage regulator
1 Device consumption requires main voltage regulator to remain powered regardless of mode
configuration
S_PDO Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted
whenever outputs of pads are forced to high impedance state or the pads power sequence driver is
switched off.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power
sequence driver is disabled. The inputs are level unchanged. In STOP mode, only pad power
sequence driver is disabled but the state of the output is kept. In STANDBY mode, the power
sequence driver and all pads except those mapped on wakeup lines are not powered and therefore
high impedance. Wakeup lines configuration remains unchanged
S_MVR Main voltage regulator status
0 Main voltage regulator is not ready
1 Main voltage regulator is ready for use
S_DFLA Data flash availability status
00 Data flash is not available
01 Data flash is in power-down mode
10 Data flash is in low-power mode
11 Data flash is in normal mode and available for use
S_CFLA Code flash availability status
00 Code flash is not available
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode and available for use
S_FMPLL frequency modulated phase locked loop status
0 frequency modulated phase locked loop is not stable
1 frequency modulated phase locked loop is providing a stable clock
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